HD64F3642AHV Datasheet, PDF (487/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

RDR—Receive data register
Appendix B Internal I/O Registers
H'FFAD
SCI3
Bit
Initial value
Read/Write
7
RDR7
0
R
6
RDR6
0
R
5
RDR5
0
R
4
RDR4
0
R
3
RDR3
0
R
2
RDR2
0
R
1
RDR1
0
R
0
RDR0
0
R
TMA—Timer mode register A
H'FFB0
Timer A
Bit
7
6
5
4
3
2
1
0
TMA7 TMA6 TMA5
—
TMA3 TMA2 TMA1 TMA0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W R/W
R/W
R/W
Clock output select
0 0 0 φ/32
1 φ/16
1 0 φ/8
1 φ/4
1 0 0 φ _W/32
1 φ _W/16
1 0 φ _W/8
1 φ _W/4
Internal clock select
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0
0
0
0 PSS
φ/8192
1 PSS
φ/4096
1
0 PSS
φ/2048
1 PSS
φ/512
1
0
0 PSS
φ/256
1 PSS
φ/128
1
0 PSS
φ/32
1 PSS
φ/8
1
0
0
0 PSW
1s
1 PSW
0.5 s
1
0 PSW
0.25 s
1 PSW
0.03125 s
1
0
0 PSW and TCA are reset
1
1
0
1
Function
Interval
timer
Time
base
Rev. 6.00 Sep 12, 2006 page 465 of 526
REJ09B0326-0600