HD64F3642AHV Datasheet, PDF (234/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Bits 2 to 0Clock Select (TMB12 to TMB10): Bits 2 to 0 select the clock input to TCB1. For
external event counting, either the rising or falling edge can be selected.
Bit 2: TMB12 Bit 1: TMB11 Bit 0: TMB10 Description
0
0
0
Internal clock: φ/8192
(initial value)
1
Internal clock: φ/2048
1
0
Internal clock: φ/512
1
Internal clock: φ/256
1
0
0
Internal clock: φ/64
1
Internal clock: φ/16
1
0
Internal clock: φ/4
1
External event (TMIB): rising or falling edge^*
Note: * The edge of the external event signal is selected by bit INTEG6 in interrupt edge select
register 2 (IEGR2). See section 3.3.2, Interrupt Control Registers, for details.
Timer Counter B1 (TCB1)
Bit
Initial value
Read/Write
7
TCB17
0
R
6
TCB16
0
R
5
TCB15
0
R
4
TCB14
0
R
3
TCB13
0
R
2
TCB12
0
R
1
TCB11
0
R
0
TCB10
0
R
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in timer
mode register B1 (TMB1). TCB1 values can be read by the CPU at any time.
When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 bit in IRR1 is
set to 1.
TCB1 is allocated to the same address as TLB1.
Upon reset, TCB1 is initialized to H'00.
Rev. 6.00 Sep 12, 2006 page 212 of 526
REJ09B0326-0600