HD64F3642AHV Datasheet, PDF (504/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
PUCR5—Port pull-up control register 5
H'FFEF
I/O ports
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PUCR5 ₇ PUCR5₆ PUCR5₅ PUCR5₄ PUCR5₃ PUCR5₂ PUCR5₁ PUCR5₀
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W R/W
R/W
R/W R/W
SYSCR1—System control register 1
H'FFF0
System control
Bit
7
6
5
4
3
2
SSBY STS2 STS1 STS0 LSON —
Initial value
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
—
1
MA1
1
R/W
0
MA0
1
R/W
Active (medium-speed)
mode clock select
0 0 φosc /16
1 φ_osc /32
1 0 φ_osc /64
1 φ osc/128
Low speed on flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ_SUB)
Standby timer select 2 to 0
0 0 0 Wait time = 8,192 states
1 Wait time = 16,384 states
1 0 Wait time = 32,768 states
1 Wait time = 65,536 states
1 _{* *} Wait time = 131,072 states
Software standby
* Don’t care
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
Rev. 6.00 Sep 12, 2006 page 482 of 526
REJ09B0326-0600