HD64F3642AHV Datasheet, PDF (136/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
6.4.5 Pin Configuration
The flash memory is controlled by means of the pins shown in table 6.6.
Table 6.6 Flash Memory Pins
Pin Name
Programming power
Mode pin
Transmit data
Receive data
Abbreviation
FVPP
TEST
TXD
RXD
Input/Output
Power supply
Input
Output
Input
Function
Apply 12.0 V
Sets H8/3644F operating mode
SCI3 transmit data output
SCI3 receive data input
The transmit data pin and receive data pin are used in boot mode.
6.4.6 Register Configuration
The registers used to control the on-chip flash memory are shown in table 6.7.
Table 6.7 Flash Memory Registers
Register Name
Flash memory control register
Erase block register 1
Erase block register 2
Abbreviation R/W
FLMCR
R/W
EBR1
R/W
EBR2
R/W
Initial Value
H'00
H'F0
H'00
Address
H'FF80
H'FF82
H'FF83
The FLMCR, EBR1, and EBR2 registers are valid only when programming and erasing flash
memory, and can only be accessed when 12 V is applied to the FV_PP pin. When 12 V is not
applied to the FV_PP pin, addresses H'FF80 to H'FF83 cannot be modified and are always read as
H'FF.
Rev. 6.00 Sep 12, 2006 page 114 of 526
REJ09B0326-0600