HD64F3642AHV Datasheet, PDF (292/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
9.6 Watchdog Timer
9.6.1 Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
Features
Features of the watchdog timer are given below.
• Incremented by internal clock source (φ/8192).
• A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times 8192/φ (from approximately 2 ms to 500 ms when φ = 4.19 MHz).
Block Diagram
Figure 9.35 shows a block diagram of the watchdog timer.
TCSRW
φ/8192
φ
PSS
TCW
Legend:
TCSRW: Timer control/status register W
TCW: Timer counter W
PSS: Prescaler S
Figure 9.35 Block Diagram of Watchdog Timer
Rev. 6.00 Sep 12, 2006 page 270 of 526
REJ09B0326-0600
Internal reset
signal