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HD64F3642AHV Datasheet, PDF (75/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
Section 2 CPU
Example 2: BSET instruction executed designating port 3
P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P30 to high-level output.
[A: Prior to executing BSET]
Input/output
Pin state
PCR3
PDR3
P37
Input
Low
level
0
1
P36
Input
High
level
0
0
P35
Output
Low
level
1
0
P34
Output
Low
level
1
0
P33
Output
Low
level
1
0
P32
Output
Low
level
1
0
P31
Output
Low
level
1
0
P30
Output
Low
level
1
0
[B: BSET instruction executed]
BSET #0 , @PDR3
[C: After executing BSET]
Input/output
Pin state
PCR3
PDR3
P37
Input
Low
level
0
0
P36
Input
High
level
0
1
The BSET instruction is executed designating port 3.
P35
Output
Low
level
1
0
P34
Output
Low
level
1
0
P33
Output
Low
level
1
0
P32
Output
Low
level
1
0
P31
Output
Low
level
1
0
P30
Output
High
level
1
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
Rev. 6.00 Sep 12, 2006 page 53 of 526
REJ09B0326-0600