HD64F3642AHV Datasheet, PDF (263/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Register Configuration
Table 9.15 shows the register configuration of timer X.
Table 9.15 Timer X Registers
Name
Abbr.
R/W
Initial Value Address
Timer interrupt enable register
Timer control/status register X
TIER
TCSRX
R/W
R/(W)^*1
H'01
H'00
H'F770
H'F771
Free-running counter H
FRCH
R/W
H'00
H'F772
Free-running counter L
Output compare register AH
Output compare register AL
Output compare register BH
Output compare register BL
FRCL
R/W
OCRAH
R/W
OCRAL
R/W
OCRBH
R/W
OCRBL
R/W
H'00
H'FF
H'FF
H'FF
H'FF
H'F773
H'F774^*2
H'F775^*2
H'F774^*2
H'F775^*2
Timer control register X
TCRX
R/W
H'00
H'F776
Timer output compare control
register
TOCR
R/W
H'E0
H'F777
Input capture register AH
ICRAH
R
H'00
H'F778
Input capture register AL
ICRAL
R
H'00
H'F779
Input capture register BH
ICRBH
R
H'00
H'F77A
Input capture register BL
ICRBL
R
H'00
H'F77B
Input capture register CH
ICRCH
R
H'00
H'F77C
Input capture register CL
ICRCL
R
H'00
H'F77D
Input capture register DH
ICRDH
R
H'00
H'F77E
Input capture register DL
ICRDL
R
H'00
H'F77F
Notes: 1. Bits 7 to 1 can only be written with 0 for flag clearing. Bit 0 is a read/write bit.
2. OCRA and OCRB share the same address. They are selected by the OCRS bit in
TOCR.
Rev. 6.00 Sep 12, 2006 page 241 of 526
REJ09B0326-0600