HD64F3642AHV Datasheet, PDF (267/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Timer Interrupt Enable Register (TIER)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE

0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W

TIER is an 8-bit read/write register that enables or disables interrupt requests.
TIER is initialized to H'01 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Input Capture Interrupt A Enable (ICIAE): Bit 7 enables or disables the ICIA interrupt
requested when ICFA is set to 1 in TCSRX.
Bit 7: ICIAE
0
1
Description
Interrupt request by ICFA (ICIA) is disabled
Interrupt request by ICFA (ICIA) is enabled
(initial value)
Bit 6Input Capture Interrupt B Enable (ICIBE): Bit 6 enables or disables the ICIB interrupt
requested when ICFB is set to 1 in TCSRX.
Bit 6: ICIBE
0
1
Description
Interrupt request by ICFB (ICIB) is disabled
Interrupt request by ICFB (ICIB) is enabled
(initial value)
Bit 5Input Capture Interrupt C Enable (ICICE): Bit 5 enables or disables the ICIC interrupt
requested when ICFC is set to 1 in TCSRX.
Bit 5: ICICE
0
1
Description
Interrupt request by ICFC (ICIC) is disabled
Interrupt request by ICFC (ICIC) is enabled
(initial value)
Rev. 6.00 Sep 12, 2006 page 245 of 526
REJ09B0326-0600