HD64F3642AHV Datasheet, PDF (155/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.7.6 Erase Flowcharts and Sample Programs
Flowchart for Erasing One Block
Section 6 ROM
Start
Set erase block register
(set bit for block to be erased to 1)
Write 0 data in all addresses to be erased
(prewrite)^*1
n=1
Enable watchdog timer ^*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms ^*5
Clear E bit
Erasing halts
Disable watchdog timer
Set block start address as
verify address
Select erase-verify mode
(EV bit = 1)
Wait (tvs1) µs ^*6
Dummy write to verify address ^*3
(flash memory latches
address)
Wait (tvs2) µs ^*6
Verify ^*4
NG
(read data H'FF?)
OK
No
Last address?
Yes
Address + 1 → address
Clear EV bit
Clear erase block register
(clear bit for erased block to 0)
End of erase
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the watchdog timer overflow interval to
the initial value shown in table 6.12.
3. For the erase-verify dummy write, write H'FF
using a byte transfer instruction.
4. For the erase-verify operation, read the data
using a byte transfer instruction. When
erasing multiple blocks, clear the erase block
register bits for erased blocks and perform
additional erasing only for unerased blocks.
5. Erase time x is successively incremented to
initial set value x 2n-1 (n = 1 to 4), and is
fixed from the 4th time onward. An initial
value of 6.25 ms or less should be set, and
the time for one erasure should be 50 ms or
less.
6. tvs1: 4 µs or more
tvs2: 2 µs or more
N: 602 (set N so that the total erase time
does not exceed 30 s)
Clear EV bit
n ≥ N? ^*6
Yes
Erase error
End of erase-verify
No
n+1→n
Yes
n > 4?
No
Double the erase time
(x × 2 → x)
Figure 6.14 Erase Flowchart
Rev. 6.00 Sep 12, 2006 page 133 of 526
REJ09B0326-0600