HD64F3642AHV Datasheet, PDF (89/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Bit 6A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter
interrupt requests.
Bit 6: IENAD
0
1
Description
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
(initial value)
Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4SCI1 Interrupt Enable (IENS1): Bit 4 enables or disables SCI1 transfer complete
interrupt requests.
Bit 4: IENS1
0
1
Description
Disables SCI1 interrupt requests
Enables SCI1 interrupt requests
(initial value)
Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
Interrupt Enable Register 3 (IENR3)
Bit
Initial value
Read/Write
7
INTEN7
0
R/W
6
INTEN6
0
R/W
5
INTEN5
0
R/W
4
INTEN4
0
R/W
3
INTEN3
0
R/W
2
INTEN2
0
R/W
1
INTEN1
0
R/W
0
INTEN0
0
R/W
IENR3 is an 8-bit read/write register that enables or disables INT₇ to INT₀ interrupt requests.
Upon reset, IENR3 is initialized to H'00.
Bits 7 to 0INT₇ to INT₀ Interrupt Enable (INTEN7 to INTEN0): Bits 7 to 0 enable or
disable INT₇ to INT₀ interrupt requests.
Bit n: INTENn
0
1
Description
Disables interrupt requests from pin INTn
Enables interrupt requests from pin INTn
(initial value)
(n = 7 to 0)
Rev. 6.00 Sep 12, 2006 page 67 of 526
REJ09B0326-0600