HD64F3642AHV Datasheet, PDF (171/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
Hardware Protection: Hardware protection refers to a state in which programming/erasing of
flash memory is forcibly suspended or disabled. At this time, the flash memory control register
(FLMCR) and erase block register (EBR1 and EBR2) settings are cleared.
Details of the hardware protection states are given below.
Functions
Item
Description
Program Erase
Verify^*1
Programming
voltage (FVPP)
protect
When 12 V is not being applied to the
FVPP pin, FLMCR, EBR1, and EBR2
are initialized, and the program/erase-
protected state is entered. To obtain
this protection, the VPP voltage should
not exceed the VCC power supply
voltage.^*3
Disabled
Disabled^*2 Disabled
Reset/standby
protect
In a reset, (including a watchdog timer Disabled
reset), and in sleep, subsleep, watch,
and standby mode, FLMCR, EBR1,
and EBR2 are initialized, and the
program/erase-protected state is
entered. In a reset via the RES pin, the
reset state is not reliably entered
unless the RES pin is held low for at
least 20 ms (oscillation settling time)^*4
after powering on. In the case of a
reset during operation, the RES pin
must be held low for a minimum of 10
system clock cycles (10φ).
Disabled^*2 Disabled
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. All blocks are erase-disabled, and individual block specification is not possible.
3. For details, see section 6.9, Flash Memory Programming and Erasing Precautions.
4. For details, see AC Characteristics in section 13, Electrical Characteristics.
6.7.9 Interrupt Handling during Flash Memory Programming/Erasing
If an interrupt is generated while the flash memory is being programmed or erased (while the P or
E bit is set in FLMCR), an operating state may be entered in which the vector will not be read
correctly in the exception handling sequence, resulting in program runaway. All interrupt sources
should therefore be masked to prevent interrupt generation while programming or erasing the flash
memory.
Rev. 6.00 Sep 12, 2006 page 149 of 526
REJ09B0326-0600