HD64F3642AHV Datasheet, PDF (119/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Power-Down Modes
5.4.2 Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A or IRQ₀) or by input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by a timer A interrupt or IRQ₀ interrupt, the mode to which a
transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If
both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0
and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to
subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2
to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared,
and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1
or the particular interrupt is disabled in the interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby
Mode.
5.4.3 Oscillator Settling Time after Watch Mode Is Cleared
The waiting time is the same as for standby mode; see section 5.3.3, Oscillator Settling Time after
Standby Mode Is Cleared.
5.5 Subsleep Mode
5.5.1 Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A is
halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-
chip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the
same states as before the transition.
Rev. 6.00 Sep 12, 2006 page 97 of 526
REJ09B0326-0600