HD64F3642AHV Datasheet, PDF (479/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

SCR1—Serial control register 1
Appendix B Internal I/O Registers
H'FFA0
SCI1
Bit
Initial value
Read/Write
7
SNC1
0
R/W
6
SNC0
0
R/W
5
MRKON
0
R/W
4
LTCH
0
R/W
3
CKS3
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select (CKS2 to CKS0)
Bit 2 Bit 1 Bit 0 _Prescaler
CKS2 CKS1 CKS0 Division
0
0
0 φ/1024
1 φ/256
1
0 φ/64
1 φ/32
1
0
0 φ/16
1 φ/8
1
0 φ/4
1 φ/2
Serial Clock Cycle
Synchronous
φ = 5 MHz φ = 2.5 MHz
204.8 µs 409.6 µs
51.2 µs
102.4 µs
12.8 µs
25.6 µs
6.4 µs
12.8 µs
3.2 µs
6.4 µs
1.6 µs
3.2 µs
0.8 µs
1.6 µs
—
0.8 µs
Clock source select (CKS3)
0 Clock source is prescaler S, and pin SCK ₁ is output pin
1 Clock source is external clock, and pin SCK₁ is input pin
LATCH TAIL select
0 HOLD TAIL is output
1 LATCH TAIL is output
TAIL MARK control
0 TAIL MARK is not output (synchronous mode)
1 TAIL MARK is output (SSB mode)
Operation mode select
0 0 8-bit synchronous transfer mode
1 16-bit synchronous transfer mode
1 0 Continuous clock output mode
1 Reserved
Rev. 6.00 Sep 12, 2006 page 457 of 526
REJ09B0326-0600