HD64F3642AHV Datasheet, PDF (373/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 A/D Converter
Bit 7A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7: ADSF
0
1
Description
Read: Indicates the completion of A/D conversion
Write: Stops A/D conversion
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
(initial value)
Bits 6 to 0Reserved Bits: Bits 6 to 0 are reserved; they are always read as 1, and cannot be
modified.
12.3 Operation
12.3.1 A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 8-bit
data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2 Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit TRGE in AMR is set to 1. Then when
the input signal edge designated in bit INTEG5 of interrupt edge select register 2 (IEGR2) is
detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion.
Figure 12.2 shows the timing.
Rev. 6.00 Sep 12, 2006 page 351 of 526
REJ09B0326-0600