HD64F3642AHV Datasheet, PDF (143/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 ROM
Boot Mode Execution Procedure: The boot mode execution procedure is shown below.
Start
1. Set the chip to boot mode and execute a reset-start.
1
Set pins to boot mode for chip
and execute reset-start
2
Host transmits H'00 data continuously
at prescribed bit rate
Chip measures low period of H'00 data
transmitted by host
3
Chip calculates bit rate and sets value
in bit rate register
After bit rate adjustment, chip transmits
4
one H'00 data byte to host to indicate
end of adjustment
2. Set the host to the prescribed bit rate (2400/4800/9600)
and have it transmit H'00 data continuously using a
transfer data format of 8-bit data plus 1 stop bit.
3. The chip repeatedly measures the low period at the
RXD pin and calculates the asynchronous
communication bit rate used by the host.
4. After SCI3 bit rate adjustment is completed, the chip
transmits one H'00 data byte to indicate the end of
adjustment.
5. On receiving the one-byte data indicating completion of
bit rate adjustment, the host should confirm normal
reception of this indication and transmit one H'55 data
byte.
Host confirms normal reception of bit rate
5
adjustment end indication, and transmits
one H'55 data byte
6. After receiving H'55, the chip transfers part of the boot
program to RAM areas H'FB80 to H'FBDF and H'FC00
to H'FF2F.
6
After receiving H'55, chip transfers part
of boot program to RAM
7. The chip branches to the RAM boot program area
(H'FC00–H'FF2F) and checks for the presence of data
written in the flash memory. If data has been written in
Chip branches to RAM boot area
(H'FC00 to H'FF2F), then checks flash
memory user area data
the flash memory, the chip erases all blocks.
8. The chip transmits one H'AA byte. The host then
transmits the number of user program bytes to be
transferred to the chip. The number of bytes should be
7
No
All data = H'FF?
sent as two bytes, upper byte followed by lower byte.
The host should then transmit sequentially the program
YES
Erase all flash
set by the user.
memory blocks^*3
The chip transmits the received byte count and user
program sequentially to the host, one byte at a time, as
verify data (echo-back).
After confirming that all flash memory
data is H'FF, chip transmits
one H'AA byte to host
8
Chip receives, as 2 bytes, number
of program bytes (N) to be transferred
to on-chip RAM^*1
9. The chip writes the received user program sequentially
to on-chip RAM area H'FBE0 to H'FF6D (910 bytes).
10. The chip transmits one H'AA byte, then branches to on-
chip RAM address H'FBE0 and executes the user
program written in area H'FBE0 to H'FF6D.
Chip transfers user program to RAM^*2
9
Chip calculates remaining
bytes to be transferred (N = N – 1)^*2
Transfer
No
end byte count
N = 0?
Yes
Chip transfers user program to RAM,
then transmits one H'AA byte to host
10
Chip branches to RAM area
address H'FBE0 and executes user
program transferred to RAM
Notes: 1. The size of the RAM area available to the user is
910 bytes. The number of bytes to be
transferred must not exceed 910 bytes. The
transfer byte count must be sent as two bytes,
upper byte followed by lower byte.
Example of transfer byte count: for 256 bytes
(H'0100), upper byte = H'01, lower byte = H'00
2. The part of the user program that controls the
flash memory should be set in the program in
accordance with the flash memory program/
erase algorithms described later in this section.
3. If a memory cell does not operate normally and
cannot be erased, the chip transmits one H'FF
byte as an erase error indication and halts the
erase operation and subsequent operations.
Figure 6.9 Boot Mode Operation Flowchart
Rev. 6.00 Sep 12, 2006 page 121 of 526
REJ09B0326-0600