HD64F3642AHV Datasheet, PDF (282/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
• Buffered input capture timing
Input capture can be buffered by using ICRC or ICRD as a buffer for ICRA or ICRB.
Figure 9.26 shows the timing when ICRA is buffered by ICRC (BUFEA = 1) and both
the rising and falling edges are selected (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and
IEDGC = 1).
φ
FTIA
Input capture
signal
FRC
n
n+1
N
N+1
ICRA
M
n
nN
ICRC
m
M
M
n
Figure 9.26 Buffered Input Capture Timing (Normal Case)
When ICRC or ICRD is used as a buffer register, the input capture flag is still set by the
selected edge of the input capture input signal. For example, if ICRC is used to buffer ICRA,
when the edge transition selected by the IEDGC bit occurs at the input capture pin, ICFC will
be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however.
In buffered operation, if the upper byte of one of the two registers that receives a data transfer
(ICRA and ICRC, or ICRB and ICRD) is being read when an input capture signal would
normally occur, the input capture signal will be delayed by one system clock (φ). Figure 9.27
shows the case when BUFEA = 1.
Rev. 6.00 Sep 12, 2006 page 260 of 526
REJ09B0326-0600