HD64F3642AHV Datasheet, PDF (510/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
IRR1—Interrupt request register 1
Bit
7
6
5
IRRTB1 IRRTA —
Initial value
0
0
0
Read/Write
R/W^* R/W^* —
H'FFF7
System control
4
3
2
1
0
—
IRRI3 IRRI2 IRRI1 IRRI0
1
0
0
0
0
—
R/W^* R/W^* R/W^* R/W^*
IRQ₃ to IRQ₀ interrupt request flag
0 [Clearing condition]
When IRRIn = 1, it is cleared by writing 0
1 [Setting condition]
When pin IRQn is set for interrupt input and the designated signal
edge is input
(n = 3 to 0)
Timer A interrupt request flag
0 [Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1 [Setting condition]
When timer counter A overflows from H'FF to H'00
Timer B1 interrupt request flag
0 [Clearing condition]
When IRRTB1 = 1, it is cleared by writing 0
1 [Setting condition]
When timer counter B1 overflows from H'FF to H'00
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Sep 12, 2006 page 488 of 526
REJ09B0326-0600