HD64F3642AHV Datasheet, PDF (295/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Bit 1Bit 0 Write Inhibit (B0WI): Bit 1 controls the writing of data to bit 0 in TCSRW.
This bit is always read as 1. Data written to this bit is not stored.
Bit 1: B0WI
0
1
Description
Bit 0 is write-enabled
Bit 0 is write-protected
(initial value)
Bit 0Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed, generating
an internal reset signal. The internal reset signal generated by the overflow resets the entire chip.
WRST is cleared to 0 by a reset from the RES pin, or when software writes 0.
Bit 0: WRST
0
1
Description
Clearing conditions:
• Reset by RES pin
(initial value)
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
Setting condition:
When TCW overflows and an internal reset signal is generated
Timer Counter W (TCW)
Bit
Initial value
Read/Write
7
TCW7
0
R/W
6
TCW6
0
R/W
5
TCW5
0
R/W
4
TCW4
0
R/W
3
TCW3
0
R/W
2
TCW2
0
R/W
1
TCW1
0
R/W
0
TCW0
0
R/W
TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input
clock is φ/8192. The TCW value can always be written or read by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
Rev. 6.00 Sep 12, 2006 page 273 of 526
REJ09B0326-0600