HD64F3642AHV Datasheet, PDF (68/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in
the case of three-state access to an on-chip peripheral module.
φ or φ _SUB
T₁ state
Bus cycle
T₂ state
T₃ state
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7 CPU States
2.7.1 Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium-
speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.
Rev. 6.00 Sep 12, 2006 page 46 of 526
REJ09B0326-0600