MC68HC08AZ32A Datasheet, PDF (98/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Table 7-2 shows the internal signal names used in this section.
Table 7-2. Signal Naming Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Buffered Version of OSC1 from Clock Generator Module (CGM)
PLL Output
PLL-based or OSC1-based clock output from CGM Module
(Bus Clock = CGMOUT divided by two)
Internal Address Bus
Internal Data Bus
Signal from the Power-on Reset Module to the SIM
Internal Reset Signal
Read/WriteSignal
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 7-2. This clock can come
from either an external oscillator or from the on-chip PLL. See Clock
Generator Module (CGM) on page 117.
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 7-2. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Technical Data
98
MC68HC08AZ32A — Rev 1.0
System Integration Module (SIM)
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