MC68HC08AZ32A Datasheet, PDF (296/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
Freescale Semiconductor, Inc.
19.3.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic one to a DDRA bit enables the output buffer
for the corresponding port A pin; a logic zero disables the output buffer.
Bit 7
6
5
4
3
2
1
Bit 0
DDRA
$0004
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-2 Data Direction Register A (DDRA)
DDRA[7:0] — Data direction register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 19-3 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
DDRAx
PTAx
PTAx
Figure 19-3. Port A I/O Circuit
Technical Data
296
MC68HC08AZ32A — Rev 1.0
I/O Ports
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