MC68HC08AZ32A Datasheet, PDF (96/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
7.9 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.9.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . 112
7.9.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . 114
7.9.3 SIM Break Flag Control Register (SBFCR). . . . . . . . . . . 115
7.2 Introduction
This section describes the system integration module, which supports up
to 24 external and/or internal interrupts. Together with the CPU, the SIM
controls all MCU activities. A block diagram of the SIM is shown in
Figure 7-1. Table 7-1 is a summary of the SIM I/O registers. The SIM is
a system state controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– STOP/WAIT/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Technical Data
96
MC68HC08AZ32A — Rev 1.0
System Integration Module (SIM)
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