MC68HC08AZ32A Datasheet, PDF (100/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter, see SIM Counter on page 104,
but an external reset does not. Each of the resets sets a corresponding
bit in the SIM reset status register (SRSR). See SIM Registers on page
112.
7.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 7-3 for details. Figure
7-3 shows the relative timing.
Reset type
POR/LVI
All others
Table 7-3. PIN Bit Set Timing
Number of cycles required to set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB PC
VECT H VECT L
Figure 7-3. External Reset Timing
Technical Data
100
MC68HC08AZ32A — Rev 1.0
System Integration Module (SIM)
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