MC68HC08AZ32A Datasheet, PDF (270/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
17.5 Interrupts
The following TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter value reaches the value in the TIMB counter modulo
registers. The TIMB overflow interrupt enable bit, TOIE, enables
TIMB overflow CPU interrupt requests. TOF and TOIE are in the
TIMB status and control register.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
17.6.1 Wait Mode
The TIMB remains active after the execution of a WAIT instruction. In
wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power
consumption by stopping the TIMB before executing the WAIT
instruction.
17.6.2 Stop Mode
The TIMB is inactive after the execution of a STOP instruction. The
STOP instruction does not affect register conditions or the state of the
TIMB counter. TIMB operation resumes when the MCU exits stop mode.
Technical Data
270
MC68HC08AZ32A — Rev 1.0
Timer Interface Module B (TIMB)
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