MC68HC08AZ32A Datasheet, PDF (152/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Break Module
Freescale Semiconductor, Inc.
10.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
10.4.3 TIM and PIT During Break Interrupts
A break interrupt stops the timer counter.
10.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_HI is present on the
RST pin.
10.5 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
Technical Data
152
MC68HC08AZ32A — Rev 1.0
Break Module
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