MC68HC08AZ32A Datasheet, PDF (237/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Transmission Formats
systems having only one master and only one slave driving the MISO
data line.
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL =’0’)
1
2
3
4
5
6
7
8
SCK (CPOL =1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
SS (TO SLAVE)
CAPTURE STROBE
Figure 16-5. Transmission Format (CPHA = ‘1’)
LSB
LSB
16.6.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = ‘1’), transmissions
are started by a software write to the SPDR. CPHA has no effect on the
delay to the start of the transmission, but it does affect the initial state of
the SCK signal. When CPHA = ‘0’, the SCK signal remains inactive for
the first half of the first SCK cycle. When CPHA = ‘1’, the first SCK cycle
begins with an edge on the SCK line from its inactive to its active level.
The SPI clock rate (selected by SPR1:SPR0) affects the delay from the
write to SPDR and the start of the SPI transmission. See Figure 16-6.
The internal SPI clock in the master is a free-running derivative of the
internal MCU clock. It is only enabled when both the SPE and SPMSTR
bits are set to conserve power. SCK edges occur halfway through the
low time of the internal MCU clock. Since the SPI clock is free-running,
it is uncertain where the write to the SPDR will occur relative to the
slower SCK. This uncertainty causes the variation in the initiation delay
shown in Figure 16-6. This delay will be no longer than a single SPI bit
time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU
bus cycles for DIV128.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
237