MC68HC08AZ32A Datasheet, PDF (256/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
1 = Overflow
0 = No overflow
MODF — Mode Fault
This clearable, ready-only flag is set in a slave SPI if the SS pin goes
high during a transmission. In a master SPI, the MODF flag is set if
the SS pin goes low at any time. Clear the MODF bit by reading the
SPI status and control register with MODF set and then writing to the
SPI data register. Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request if the SPTIE bit in the SPI control register
is set also.
NOTE: The SPI data register should not be written to unless the SPTE bit is
high.
For an idle master or idle slave that has no data loaded into its
transmit buffer, the SPTE will be set again within two bus cycles since
the transmit buffer empties into the shift register. This allows the user
to queue up a 16-bit value to send. For an already active slave, the
load of the shift register cannot occur until the transmission is
completed. This implies that a back-to-back write to the transmit data
register is not possible. The SPTE indicates when the next write can
occur.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
Technical Data
256
MC68HC08AZ32A — Rev 1.0
Serial Peripheral Interface (SPI)
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