MC68HC08AZ32A Datasheet, PDF (111/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Low-Power Modes
7.8.2 STOP mode
In STOP mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from
STOP mode. Stacking for interrupts begins after the selected STOP
recovery time has elapsed. Reset also causes an exit from STOP mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in STOP mode, stopping the CPU and peripherals. STOP
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, STOP recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long start-up
times from STOP mode.
NOTE: External crystal applications should use the full STOP recovery time by
clearing the SSREC bit.
The break module is inactive in STOP mode. The STOP instruction does
not affect break module register states.
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of STOP recovery. It is then used to time
the recovery period. Figure 7-13 shows STOP mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-13. STOP Mode Entry Timing
MC68HC08AZ32A — Rev 1.0
MOTOROLA
System Integration Module (SIM)
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Technical Data
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