MC68HC08AZ32A Datasheet, PDF (175/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low Voltage Inhibit (LVI)
Functional Description
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM MORA
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
ANLGTRIP
Stop Mode
Filter Bypass
LVISTOP
FROM MORA
LVIOUT
FROM MORA
LVIRST
Figure 13-1. LVI Module Block Diagram
Table 13-1. LVI I/O Register Summary
Register Name
Bit 7 6
5
4
3
2
LVI Status Register (LVISR) LVIOUT
= Unimplemented
LVI RESET
1 Bit 0 Addr.
$FE0F
13.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the mask option
register, the LVIPWR bit must be at logic ‘1’ to enable the LVI module
and the LVIRST bit must be at logic ‘0’ to disable LVI resets.
13.4.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls to the LVI_TRIPF level and remains at or below that level for 9 or more
consecutive CPU cycles. In the mask option register, the LVIPWR and
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Low Voltage Inhibit (LVI)
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Technical Data
175