MC68HC08AZ32A Datasheet, PDF (104/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
NOTE:
Extra care should be exercised if code in this part has been taken
from another HC08 with a different memory map since some legal
addresses could become illegal addresses on a smaller ROM. It is
the user’s responsibility to check their code for illegal addresses.
Older HC08s may have a different illegal address reset
specification.
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the LVI_TRIPF voltage. The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the RST pin for all
internal reset sources.
7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
STOP mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly (COP) module. The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
7.5.1 SIM Counter During Power-On Reset
The power-on reset (POR) module detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
Technical Data
104
MC68HC08AZ32A — Rev 1.0
System Integration Module (SIM)
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