MC68HC08AZ32A Datasheet, PDF (252/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
16.13.1 SPI Control Register (SPCR)
The SPI control register does the following:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
• Enables the SPI module
Bit 7
6
5
4
3
2
1
SPCR
Read:
SPRIE
R
SPMSTR CPOL CPHA SPWOM SPE
Write:
Reset: 0
0
1
0
1
0
0
R
= Reserved
Figure 16-12. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
Technical Data
252
MC68HC08AZ32A — Rev 1.0
Serial Peripheral Interface (SPI)
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