MC68HC08AZ32A Datasheet, PDF (114/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
7.9.2 SIM Reset Status Register (SRSR)
This register contains six flags that show the source of the last reset. The
SIM reset status register can be cleared by reading it. A power-on reset
sets the POR bit and clears all other bits in the register.
Bit 7
6
5
4
3
2
1
Bit 0
SRSR ^{Read: POR}
PIN
COP ILOP ILAD
0
LVI
0
$FE01 _Write:
POR:
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-16. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
Technical Data
114
MC68HC08AZ32A — Rev 1.0
System Integration Module (SIM)
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