MC68HC08AZ32A Datasheet, PDF (49/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Memory Map
Additional Status and Control Registers
2.4 Additional Status and Control Registers
Selected addresses in the range $FE00 to $FFCB contain additional
Status and Control registers as shown in Figure 2-3. A noted exception
is the COP Control Register (COPCTL) at address $FFFF.
Addr.
Name
Bit 7
6
5
4
3
2
1
$FE00
SIM Break Status Register
(SBSR)
R:
W:
R
R
R
R
R
R
BW
0
$FE01
SIM Reset Status Register
(SRSR)
R:
W:
POR
PIN
COP
ILOP
ILAD
0
LVI
$FE03
SIM Break Flag Control R:
Register (SBFCR) W:
BCFE
R
R
R
R
R
R
$FE09
Mask Option Register B
R:
EEDIVCL
K
(MORB) _{W: R}
R
EESEC
EEMONSE
C
AZ32A
R
R
R
R
R
$FE0C
Break Address Register R:
High (BRKH) W:
Bit 15
14
13
12
11
10
9
$FE0D
Break Address Register R:
Low (BRKL) W:
7
6
5
4
3
2
1
$FE0E
Break Status and Control R:
Register (BRKSCR) W:
BRKE
BRKA
0
0
0
0
0
$FE0F LVI Status Register (LVISR)
R:
W:
LVIOUT
0
0
0
0
0
0
$FE10
EEDIV High Non-volatile R: EEDIV
Register (EEDIVHNVR) W: SECD
R
R
R
R EEDIV10 EEDIV9
$FE11
EEDIV Low Non-volatile
Register (EEDIVLNVR)
R:
W:
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3 EE2DIV EEDIV1
$FE1A
EEDIV Divider High R: _EEDIV
0
Register (EEDIVH) ^{W: SECD}
0
0
0
EEDIV10 EEDIV9
$FE1B
EEDIV Divider Low
Register (EEDIVL)
R:
W:
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3 EE2DIV EEDIV1
$FE1C
EENVR
R:
W: ^R
R
R EEPRTCT EEPB3 EEPB2 EEPB1
$FE1D
EECR
R:
W:
R
0
EEOFF EERAS1 EERAS0 ELAT AUTO
$FE1F
EEACR
R: R
R
R EEPRTCT EEBP3 EEBP2 EEBP1
W:
$FFFF
COP Control Register R:
(COPCTL) W:
LOW BYTE OF RESET VECTOR
WRITING TO $FFFF CLEARS COP COUNTER
Bit 0
R
0
R
R
8
0
0
0
EEDIV8
EEDIV0
EEDIV8
EEDIV0
EEPB0
EEPGM
EEBP0
= Unimplemented
R = Reserved
Figure 2-3. Additional Status and Control Registers
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Memory Map
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Technical Data
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