MC68HC08AZ32A Datasheet, PDF (366/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
aborted due to a pending abort request (see Transmit Buffer
Priority Registers on page 352). If not masked, a receive interrupt is
pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag
(ABTAK, see above). When a TXEx flag is set, the corresponding
ABTRQx bit (ABTRQ, see MSCAN08 Transmitter Control Register)
is cleared.
1 = The associated message buffer is empty (not scheduled).
0 = The associated message buffer is full (loaded with a message
due for transmission).
NOTE: To ensure data integrity, no registers of the transmit buffers should be
written to while the associated TXE flag is cleared.
NOTE: The CTFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
20.14.8 MSCAN08 Transmitter Control Register
Technical Data
366
Address: $0507
Bit 7
6
5
4
3
2
1
Read: 0
0
ABTRQ2 ABTRQ1 ABTRQ0
Write:
TXEIE2 TXEIE1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 20-22. Transmitter Control Register (CTCR)
Bit 0
TXEIE0
0
ABTRQ2–ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that an already scheduled
message buffer (TXE = 0) be aborted. The MSCAN08 will grant the
request if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a
message is aborted the associated TXE and the abort acknowledge
flag (ABTAK) (see MSCAN08 Transmitter Flag Register on page
MC68HC08AZ32A — Rev 1.0
MSCAN08 Controller (MSCAN08)
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