MC68HC08AZ32A Datasheet, PDF (185/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
IRQ Status and Control Register (ISCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic ‘1’ to this write-only bit clears the IRQ latch. ACK
always reads as logic ‘0’. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic ‘1’ to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
MC68HC08AZ32A — Rev 1.0
MOTOROLA
External Interrupt Module (IRQ)
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Technical Data
185