MC68HC08AZ32A Datasheet, PDF (395/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Timer Interface Module A (TIMA)
Interrupts
22.5 Interrupts
The following TIMA sources can generate interrupt requests:
• TIMA overflow flag (TOF) — The TOF bit is set when the TIMA
counter reaches the modulo value programmed in the TIMA
counter modulo registers. The TIMA overflow interrupt enable bit,
TOIE, enables TIMA overflow CPU interrupt requests. TOF and
TOIE are in the TIMA status and control register.
• TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
22.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
22.6.1 Wait Mode
The TIMA remains active after the execution of a WAIT instruction. In
wait mode, the TIMA registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
If TIMA functions are not required during wait mode, reduce power
consumption by stopping the TIMA before executing the WAIT
instruction.
22.6.2 Stop Mode
The TIMA is inactive after the execution of a STOP instruction. The
STOP instruction does not affect register conditions or the state of the
TIMA counter. TIMA operation resumes when the MCU exits stop mode.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Timer Interface Module A (TIMA)
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Technical Data
395