MC68HC08AZ32A Datasheet, PDF (183/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
Functional Description
14.4.1 IRQ Pin
A ‘0’ on the IRQ pin can latch an interrupt request into the IRQ latch. A
vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-
level-sensitive. With MODE set, both of the following actions must occur
to clear the IRQ latch:
• Vector fetch or software clear — a vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic ‘1’ to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ pin and require
software to clear the IRQ latch. Writing to the ACK bit can also
prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge that
occurs after writing to the ACK bit latches another interrupt
request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
• Return of the IRQ pin to logic ‘1’ — as long as the IRQ pin is at
logic ‘0’, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic
‘1’ may occur in any order. The interrupt request remains pending as
long as the IRQ pin is at logic ‘0’. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
The BIH or BIL instruction is used to read the logic level on the IRQ pin.
NOTE: When using the level-sensitive interrupt trigger, false interrupts can be
avoided by masking interrupt requests in the interrupt routine.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
External Interrupt Module (IRQ)
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Technical Data
183