MC68HC08AZ32A Datasheet, PDF (169/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Computer Operating Properly (COP)
I/O Signals
MORA. When COPRS = 0, a 4.9152 MHz crystal, gives a COP timeout
period of 53.3ms. Writing any value to location $FFFF before overflow
occurs prevents a COP reset by clearing the COP counter and stages 4
through 12 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR). See SIM Reset Status
Register (SRSR) on page 114.
NOTE:
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held
at V_Hi. During the break state, V_Hi on the RST pin disables the COP.
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
12.4 I/O Signals
The following paragraphs describe the signals shown in Figure 12-1.
12.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. The CGMXCLK
frequency is equal to the crystal frequency.
12.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Computer Operating Properly (COP)
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Technical Data
169