MC68HC08AZ32A Datasheet, PDF (208/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
15.6.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. Any enabled CPU interrupt request from the
SCI module does not bring the MCU out of Stop mode. SCI module
operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
15.7 SCI During Break Module Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
149).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
15.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
• PTE0/TxD — Transmit data
• PTE1/RxD — Receive data
Technical Data
208
MC68HC08AZ32A — Rev 1.0
Serial Communications Interface (SCI)
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