MC68HC08AZ32A Datasheet, PDF (124/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Technical Data
124
These conditions apply when the PLL is in automatic bandwidth control
mode:
• The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a
read-only indicator of the mode of the filter. See Acquisition and
Tracking Modes on page 123.
• The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆_trk, and is cleared when the VCO frequency is out of a
certain tolerance, ∆_unt. See Electrical Specifications on page 423.
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆_Lock, and is cleared when the VCO frequency is out of a
certain tolerance, ∆_unl. See Electrical Specifications on page 423.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. See PLL Control
Register on page 131.
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below f_busmax and
require fast startup. The following conditions apply when in manual
mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, t_acq (see Electrical Specifications on page 423), after
turning on the PLL by setting PLLON in the PLL control register
(PCTL).
• Software must wait a given time, t_al, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
MC68HC08AZ32A — Rev 1.0
Clock Generator Module (CGM)
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