MC68HC08AZ32A Datasheet, PDF (148/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Mask Options
Freescale Semiconductor, Inc.
Bit 7
6
5
4
3
2
1
Bit 0
MORB
$FE09
Read: EEDIVCLK
Write:
R
R
EESEC EEMONSEC AZ32A
R
R
R
Reset:
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 9-2. Mask Option Register B (MORB)
EEDIVCLK — EEPROM Timebase Divider Clock Select Bit
EEDIVCLK selects the reference clock source for the EEPROM
timebase divider. See EEPROM Timebase Divider Register on
page 72.
1 = CPU bus clock drives the EEPROM timebase divider
0 = CGMXCLK drives the EEPROM timebase divider
EESEC — This read/write bit has no function.
1 = N/A
0 = N/A
EEMONSEC — EEPROM Read Protection in Monitor Mode Bit
When EEMONSEC is set the entire EEPROM aray cannot be
acessed in monitor mode unless a valid security code is entered.
1 = EEPROM read protection in monitor mode enabled.
0 = EEPROM read protection in monitor mode disabled.
AZ32A — Device Indicator
This bit is used to distinguish a MC68HC08AZ32A from older non-’A’
suffix versions
1 = ‘A’ version
0 = Non-’A’ version
Extra care should be exercised when selecting mask option
registers since other HC08 family parts may have different options.
If in doubt, check with your local field applications representative.
Technical Data
148
MC68HC08AZ32A — Rev 1.0
Mask Options
For More Information On This Product,
Go to: www.freescale.com
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