MC68HC08AZ32A Datasheet, PDF (240/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
2
5
READ SPDR
3
7
1 BYTE 1 SETS SPRF BIT.
5 CPU READS SPSCRW WITH SPRF BIT SET
2 ^{CPU READS SPSCR WITH SPRF BIT SET}
AND OVRF BIT CLEAR.
AND OVRF BIT CLEAR.
6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 BYTE 2 SETS SPRF BIT.
7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF
BUT NOT OVRF BIT.
8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 16-7. Missed Read of Overflow Condition
The first part of Figure 16-7 shows how to read the SPSCR and SPDR
to clear the SPRF without problems. However, as illustrated by the
second transmission example, the OVRF flag can be set in the interval
between SPSCR and SPDR being read.
In this case, an overflow can easily be missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it will not be
obvious that bytes are being lost as more transmissions are completed.
To prevent this, the OVRF interrupt should be enabled, or alternatively
another read of the SPSCR should be carried out following the read of
the SPDR. This ensures that the OVRF was not set before the SPRF
was cleared and that future transmissions will terminate with an SPRF
interrupt. Figure 16-8 illustrates this process. Generally, to avoid this
second SPSCR read, enable the OVRF to the CPU by setting the ERRIE
bit.
Technical Data
240
MC68HC08AZ32A — Rev 1.0
Serial Peripheral Interface (SPI)
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