MC68HC08AZ32A Datasheet, PDF (427/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Electrical Specifications
Control Timing
Monitor Mode Entry Voltage on IRQ
(see Note 10)
V_HI
V_DD + 3
V_DD + 4.5
V
1.V_DD = 5.0 Vdc ± 0.5v, V_SS = 0 Vdc, T_A = –40 °C to T_{A (MAX)}, unless otherwise noted.
2.Run (Operating) I_DD measured using external square wave clock source (f_BUS = 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
tance linearly affects run I_DD. Measured with all modules enabled.
3.Wait I_DD measured using external square wave clock source (f_BUS = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait I_DD. Measured with all modules enabled.
4.Stop I_DD measured with OSC1 = V_SS.
5.Maximum is highest voltage that POR is guaranteed.
6.Maximum is highest voltage that POR is possible.
7.If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum V_DD is reached.
8.See Computer Operating Properly (COP) on page 167. V_HI applied to RST.
9.Although I_DD is proportional to bus frequency, a current of several mA is present even at very low frequencies.
10.See monitor mode description within Computer Operating Properly (COP) on page 167. V_HI applied to IRQ or RST.
11.When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit recov-
erable leakage values within the specification indicated.
24.6 Control Timing
Characteristic
Bus Operating Frequency (4.5–5.5 V — V_DD Only)
Internal Clock Period (1/f_BUS)
RESET Pulse Width Low
IRQ Interrupt Pulse Width Low (Edge-Triggered)
IRQ Interrupt Pulse Period
Symbol
f_BUS
t_cyc
t_RL
t_ILHI
t_ILIL
Min
—
119
1.5
1.5
Note 3
Max
8.4
—
—
—
—
Unit
MHz
ns
t_cyc
t_cyc
t_cyc
16-Bit Timer
Input Capture Pulse Width (see Note 2)
Input Capture Period
Input Clock Pulse Width
t_TH, t_TL
2
—
t_cyc
t_TLTL
Note 3
—
t_cyc
t_TCH, t_TCL ^(1/fOP^{) + 5}
—
ns
MSCAN Wake-up Filter Pulse Width (see Note 4)
t_WUP
2
5
µs
1.V_DD = 5.0 Vdc ± 0.5v, V_SS = 0 Vdc, T_A = –40 °C to T_{A (MAX)}, unless otherwise noted.
2.Refer to Table 17-2 and Table 22-2 and supporting notes.
3.The minimum period t_TLTL or t_ILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus t_cyc.
4. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Electrical Specifications
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Technical Data
427