MC68HC08AZ32A Datasheet, PDF (308/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
Freescale Semiconductor, Inc.
MISO — Master In/Slave Out
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. See SPI Control Register (SPCR) on page 252.
SS — Slave Select
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. See SPI Control Register (SPCR) on page 252. When the SPI
is enabled as a slave, the DDRF0 bit in data direction register E
(DDRE) has no effect on the PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 19-6.
TACH[1:0] — Timer A Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. See TIMA
Channel Status and Control Registers on page 402.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIMA. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 19-6.
Technical Data
308
MC68HC08AZ32A — Rev 1.0
I/O Ports
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