MC68HC08AZ32A Datasheet, PDF (313/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
I/O Ports
Port F
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1-PTF4/TBCH0 pins are the TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1-PTF4/TBCH0
pins are timer channel I/O pins or general purpose I/O pins. See TIMB
Status and Control Register on page 273.
NOTE:
Data direction register F(DDRF) does not affect the data direction of port
F pins that are being used by TIMA and TIMB. However, the DDRF bits
always determine whether reading port F returns the states of the
latches or the states of the pins. See Table 19-7.
19.8.2 Data Direction Register F (DDRF)
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic one to a DDRF bit enables the output buffer
for the corresponding port F pin; a logic zero disables the output buffer.
DDRF
$000D
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write: R
Reset:
0
0
0
0
0
0
0
R = Reserved
Figure 19-17. Data Direction Register F (DDRF)
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
I/O Ports
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Technical Data
313