MC68HC08AZ32A Datasheet, PDF (153/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Break Module
Break Module Registers
10.5.1 Break Status and Control Register (BRKSCR)
The break status and control register contains break module enable and
status bits.
Bit 7
6
5
4
3
2
1
Bit 0
BRKSCR
$FE0E
Read:
Write:
BRKE
BRKA
0
0
0
0
0
0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-2. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
BRKE is cleared by writing a ‘0’ to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a ‘1’ to BRKA generates a break interrupt.
BRKA is cleared by writing a ‘0’ to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Break Module
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Technical Data
153