MC68HC08AZ32A Datasheet, PDF (247/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Low-Power Modes
16.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
16.10.1 WAIT Mode
The SPI module remains active after the execution of a WAIT instruction.
In WAIT mode the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of WAIT mode.
If SPI module functions are not required during WAIT mode, power
consumption can be reduced by disabling the SPI module before
executing the WAIT instruction.
To exit WAIT mode when an overflow condition occurs, the OVRF bit
should be enabled to generate CPU interrupt requests by setting the
error interrupt enable bit (ERRIE). See Interrupts on page 243.
16.10.2 STOP Mode
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after an external interrupt. If STOP mode is exited by reset, any
transfer in progress is aborted, and the SPI is reset.
16.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See SIM Break Flag Control
Register (SBFCR) on page 115.
To allow software to clear status bits during a break interrupt, a ‘1’ should
be written to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
247