MC68HC08AZ32A Datasheet, PDF (251/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
I/O Registers
to the SPI regardless of the state of the data direction register of the
shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register. See Table 16-
4.
Table 16-4. SPI Configuration
SPE SPMSTR MODFEN SPI CONFIGURATION
0
X
X
Not Enabled
1
0
X
Slave
1
1
0
Master without MODF
1
1
X = don’t care
1
Master with MODF
STATE OF SS LOGIC
General-purpose I/O; SS
ignored by SPI
Input-only to SPI
General-purpose I/O; SS
ignored by SPI
Input-only to SPI
16.12.5 V_SS
(Clock Ground)
V_SS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the V_SS pin.
16.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
MC68HC08AZ32A — Rev 1.0
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
251