MC68HC08AZ32A Datasheet, PDF (106/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
processing can resume. Figure 7-7 shows interrupt entry timing, and
Figure 7-8 shows interrupt recovery timing.
.
MODULE
INTERRUPT
I-bit
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H
VECT L START ADDRESS
IDB
DUMMY ^{PC–1[7:0]} PC–1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
R/W
Figure 7-7. Interrupt Entry
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
until the latched interrupt is serviced (or the I-bit is cleared). See Figure
7-8.
MODULE
INTERRUPT
I-BIT
IAB
IDB
R/W
SP – 4 SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC–1[15:8] OPCODE OPERAND
Figure 7-8. Interrupt Recovery
Technical Data
106
MC68HC08AZ32A — Rev 1.0
System Integration Module (SIM)
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