MC68HC08AZ32A Datasheet, PDF (367/456 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
Programmer’s Model of Control Registers
365) will be set and an TXE interrupt is generated if enabled. The
CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever
the associated TXE flag is set.
1 = Abort request pending
0 = No abort request
NOTE: The software must not clear one or more of the TXE flags in CTFLG and
simultaneously set the respective ABTRQ bit(s).
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable
1 = A transmitter empty (transmit buffer available for transmission)
event results in a transmitter empty interrupt.
0 = No interrupt is generated from this event.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
20.14.9 MSCAN08 Identifier Acceptance Control Register
Address: $0508
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
0
IDAM1 IDAM0
0
IDHIT1 IDHIT0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-23. Identifier Acceptance Control Register (CIDAC)
IDAM1–IDAM0— Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organization (see Identifier Acceptance Filter on page 330). Table
20-9 summarizes the different settings. In “filter closed” mode no
messages will be accepted so that the foreground buffer will never be
reloaded.
MC68HC08AZ32A — Rev 1.0
MOTOROLA
MSCAN08 Controller (MSCAN08)
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Technical Data
367